Products

Design Cores

IntelliProp has a basic design philosophy that values design reuse. Many of the design cores are heavily leveraged previous designs. In addition to making use of design reuse, all IntelliProp Inc. cores are fully verified via psuedo-random simulation. This design philosophy allows IntelliProp to develop very stable design cores that are easily integrated into customer designs.

S-ATA - The IPC102SA is an RTL core implementing a S-ATA2 interface intended to be integrated into a system-on-a-chip ASIC. The protocol interface is compliant to the S-ATA2 specification as defined by the Serial ATA International Organization.

SAS - The IPC102SS is an RTL core implementing a Serial Attached SCSI (SAS) interface intended to be integrated into a system-on-a-chip ASIC. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization.

SAS/S-ATA Dual Boot - The IPC102SD is an RTL core implementing a dual boot S-ATA and Serial Attached SCSI (SAS) interface intended to be integrated into a system-on-a-chip ASIC. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization and the S-ATA2 specification as defined by the Serial ATA International Organization.

CE-ATA - The IPC100CE is an RTL core implementing a CE-ATA or a MMC-ATAT device interface. The IPC100MC is an RTL core implementing a CE-ATA or a MMC-ATA host interface. Both cores are intended to be integrated into system-on-a-chip ASIC's. The protocol interface is compliant to the CE-ATA specification as defined by the CE-ATA consortium as well as the ATA over MMC specification.

CF+/IDE - The IPC100AT is an RTL core implementing an ATA interface intended to be integrated into a system-on-a-chip ASIC for Compact Flash+ or IDE applications. The protocol interface is compliant to the ATA, revision 7 specification and the Compact Flash specification.