RTL Storage Interface Cores

IntelliProp Inc. also provides industry-proven RTL storage interface cores. Initially developed as a mechanism to develop and validate IntelliProp eVCs, these cores have undergone extensive testing and rigorous verification through pseudo-ramdom simulation.  Additionally, the cores have been synthesized to FPGA prototypes which are currently being used and tested by major disk drive manufacturers.

IPR-SA100C/IPR-SA150C:  SATA Host and Device Cores
The IPR-SA100C is an RTL core implementing a SATA3 host interface intended to be integrated into a system-on-a-chip ASIC. The IPR-SA150C is an RTL core implementing a SATA3 device interface.  The protocol interface is compliant to the SATA3 specification as defined by the Serial ATA International Organization.
Request SATA Host and Device Cores datasheet...>

IPR-SS100C/IPR-SS150C: SAS Initiator and SAS Target Cores
The IPR-SS100C is an RTL core implementing a Serial Attached SCSI (SAS) initiator interface intended to be integrated into a system-on-a-chip ASIC. The IPR-SS150C is an RTL core implementing a SAS target interface.  The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization.
Request SAS Target Cores datasheet...>

IPR-SARD100CF: SATA RAID Core
The IPR-SARD100CF is a hardware design block written in HDL that performs RAID 0 and RAID 1 operations to provide either higher performance access to disks or uninterrupted data access even with disk failure. The IntelliProp RAID IP Core introduces very little latency to issue commands and to transfer data between the SATA storage devices and the backend data interface. The RAID IP Core is designed to exist within a customer’s larger design to provide RAID performance availability and reliability advantages.
Request SATA RAID Core datasheet...>

IPR-CF100C/IPR-CF200C:  ATA/CF+ (True IDE) Host and Device Cores
The IPR-CF100C is an RTL core implementing an ATA host interface intended to be integrated into a system-on-a-chip ASIC for Compact Flash+ or IDE applications. The IPR-CF200C is an RTL core implementing an ATA device interface.  The protocol interface is compliant to the ATA, revision 7 specification and the Compact Flash specification.
Request Host and Device Cores datasheet...>

IPR-CE100C/IPR-CE200C:  CE-ATA Host and Device Cores
The IPR-CE200C is an RTL core implementing a CE-ATA or a MMC-ATA device interface. The IPR-CE100C is an RTL core implementing a CE-ATA or a MMC-ATA host interface. Both cores are intended to be integrated into system-on-a-chip ASIC's. The protocol interface is compliant to the CE-ATA specification as defined by the CE-ATA consortium as well as the ATA over MMC specification.
Request CE-ATA Host and Device Cores datasheet...>