The IntelliProp IPC-BL120A-ZM AES-XTS Encryption IP Core is a production-hardened security engine designed to provide high-speed, hardware-based data encryption and decryption for storage applications. Implementing the IEEE 1619-2007 standard, the core utilizes Advanced Encryption Standard in XEX-based Tweaked-codebook mode with Ciphertext Stealing (AES-XTS) to secure sector-based data at rest without performance degradation.
Engineered to operate seamlessly inline within host storage datapaths, the IPC-BL120A-ZM handles data encryption directly in hardware logic, ensuring maximum line-rate throughput and ultra-low latency. The core supports both 128-bit and 256-bit key sizes (AES-XTS-128 and AES-XTS-256) and is optimized for direct integration into NVMe, SATA, PCIe, and custom storage controller architectures.
Delivered as fully synchronous, high-quality RTL, the IPC-BL120A-ZM offers flexible bus interface options and low gate-count utilization, enabling straightforward timing closure and rapid integration across modern FPGA fabrics and custom ASIC designs.
Features
- Standards Compliance: Fully compliant with IEEE 1619-2007 (AES-XTS) specifications and NIST FIPS 197 standards for storage encryption at rest.
- Strong Cryptographic Key Support: Supports both AES-XTS 128-bit and 256-bit key lengths (256-bit and 512-bit total XTS key material).
- Inline High-Throughput Processing: Fully pipelined hardware datapath delivers deterministic, line-rate encryption and decryption at high clock speeds.
- Low-Latency Operation: Minimized pipeline depth ensures high-bandwidth throughput with zero CPU performance impact or latency bottlenecks.
- Configurable Data Bus Widths: Flexible interface options supporting standard 32-bit, 64-bit, 128-bit, or 256-bit streaming and memory-mapped system buses.
- Sector and LBA Tweak Management: Integrated hardware handling of Logical Block Addressing (LBA) and sector tweaks for seamless storage sector alignment.
- Broad Storage Integration: Optimized for direct inline placement in NVMe, SATA, SAS, PCIe storage bridges, and secure SSD controllers.
- Synchronous Synthesizable RTL: Delivered as clean, fully synchronous Verilog source code or netlist for rapid placement, routing, and predictable timing closure on FPGAs and ASICs.
Deliverables
- Production-Ready Maturity: Extensively verified using a coverage-driven methodology in pseudo-random simulation environments.
- Flexible Delivery: Fully synthesizable RTL optimized for clean timing closure across modern FPGA and custom ASIC architectures.
- 100% U.S.-Based Engineering: All design, technical integration, and post-sales support are handled directly by our primary engineering teams operating out of our Longmont, Colorado facilities.
- Defense-Industry Compliant: Development workflow and documentation adhere to standards required for U.S. defense, aerospace, and ITAR-controlled integration.
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Archived view: https://intellipropipcores.com/ipc-bl120-zm/