Full RTL design in Verilog and VHDL for FPGA, Structured ASIC, and full-custom ASIC targets. Our engineers work within your design flow — or provide the complete flow — across any major process node (TSMC, GlobalFoundries, Samsung).
Protocol-level verification using constrained-random stimulus generation, functional coverage analysis, and regression testing. Verification languages: SystemVerilog, E, VERA, SystemC. IntelliProp's SATA and SAS cores are third-party certified with partner SERDES — the same methodology applies to customer engagements.
Licensed an IntelliProp IP core? Our engineers can embed directly to complete integration into your design — covering clocking, reset, bus fabric hookup, timing closure, and bring-up support. Available as a fixed-price engagement or time-and-materials.
FPGA bring-up and prototyping across Intel PSG (Stratix, Arria), Xilinx/AMD (Virtex, Kintex, UltraScale), Achronix, and Lattice platforms. Reference bitstreams and board support packages available for common development boards.
Architecture review, protocol selection, and feasibility analysis for designs involving CXL, NVMe, SATA, SAS, Gen-Z, PCIe, or RAID. IntelliProp's engineers have contributed directly to standards development — an advantage that translates into concrete implementation guidance.
Need a protocol variant, performance optimization, or entirely new IP core not in the catalog? IntelliProp develops custom IP under NDA with full RTL source and testbench delivery. All custom IP follows the same silicon-proven verification methodology as the standard catalog.
IntelliProp engineers work within your design environment — your tools, your version control, your stand-ups. We don't produce recommendations and leave. We deliver working RTL, passing regressions, and signed-off coverage reports.
Engagements range from short-term verification sprints to multi-year embedded design partnerships. Most begin with a scoping call followed by a fixed-scope statement of work — typically delivered within two weeks of initial contact.
We review your design requirements, timeline, and target platform. No NDA required for initial discussion.
Fixed-scope SOW or time-and-materials agreement. NDA executed. Access to your repo and tools provisioned.
IntelliProp engineers join your team. Daily collaboration, weekly progress reports, milestone-gated deliverables.
Code review, coverage closure, regression clean. Deliverables handed off with documentation and support window.
Our engineers have designed, verified, and taped out IP for every major memory and storage protocol. This isn't familiarity — it's the same knowledge base behind 35+ silicon-proven cores.
Compute Express Link 1.1 / 2.0 / 3.0. Fabric management, memory controller, composability. Foundation of the Omega platform.
NVMe 1.3 / 1.4. Host accelerator, target IP, NVMe-to-NVMe and NVMe-to-SATA bridge designs. PCIe endpoint integration.
SATA I/II/III. Host app, AHCI, device ADCI, Y-bridge, port multiplier. Third-party certified with partner SERDES.
SAS 1.0 / 2.0 / 3.0. Initiator, target, speed bridge. RAID-0 ready. Third-party certified with partner SERDES.
Gen-Z 1.0. Requester, responder, switch, ZMMU, link layer, physical layer for 802.3 and PCIe.
PCIe 3.0 / 4.0 / 5.0. Root complex, endpoint, switch. Used as physical layer for NVMe, CXL, and Gen-Z overlays.
AES-XTS, AES-GCM, AES-CTR hardware datapaths. BCH ECC. Inline encryption for storage and memory controllers.
RAID-0 production-ready, extensible architecture toward RAID-5. Paired with SATA and NVMe host cores.
ONFI 3.0, Toggle, async flash controller. Raw NAND management for SSD and storage product designs.
Most contract engineering firms hire generalists and ramp up on your protocol. IntelliProp engineers have shipped production silicon in these protocols — that knowledge arrives on day one.
We are also active participants in the standards bodies that define these protocols — CXL Consortium, PCI-SIG, JEDEC, NVM Express, ONFI, and SATA-IO. When a spec is ambiguous, we know who to call.
