AES-GCM Encryption IP Core

The IntelliProp IPC-BL193A-ZM AES-GCM Encryption IP Core is a production-hardened cryptographic hardware module designed to deliver high-speed, authenticated data encryption and decryption. Implementing the Galois/Counter Mode (GCM) of operation as specified in NIST SP 800-38D, the core provides both confidentiality and data integrity verification (authentication tagging) in a single, high-efficiency hardware engine.

Engineered to operate seamlessly inline within network datapaths and high-speed storage architectures, the IPC-BL193A-ZM handles full payload encryption and MAC tag generation directly in dedicated hardware logic. Supporting both 128-bit and 256-bit key sizes (AES-GCM-128 and AES-GCM-256), the core is optimized for demanding applications including MACsec, IPsec, NVMe-over-Fabrics (NVMe-oF), and secure SoC bus interconnects.

Delivered as fully synchronous, production-ready RTL, the IPC-BL193A-ZM features a pipelined, high-throughput design with flexible data bus options, enabling predictable timing closure and low gate utilization across leading FPGA fabrics and custom ASIC technologies.

Features

• Standards Compliance: Fully compliant with NIST SP 800-38D (Galois/Counter Mode) and NIST FIPS 197 Advanced Encryption Standard (AES) specifications.
• Combined Cryptographic Services: Provides simultaneous high-speed confidentiality (AES counter mode encryption) and data authenticity/integrity protection (Galois MAC generation).
• Strong Key Length Support: Fully supports both 128-bit and 256-bit AES key lengths for enterprise and defense-grade security compliance.
• Pipelined Line-Rate Architecture: High-throughput, fully pipelined datapath maintains deterministic line-rate performance with minimal latency overhead.
• Flexible Data Bus Interfaces: Scalable bus interfaces supporting standard 32-bit, 64-bit, 128-bit, or 256-bit streaming data structures.
• AAD & Tag Processing: Hardware-accelerated processing of Additional Authenticated Data (AAD) and automatic generation/verification of 128-bit authentication tags.
• Broad Application Suitability: Ideal for deployment in MACsec/IPsec network security, NVMe-oF datapaths, secure memory controllers, and cloud infrastructure security.
• Synchronous Synthesizable RTL: Delivered as clean, fully synchronous Verilog source code or netlist optimized for rapid placement, routing, and timing closure across modern FPGAs and ASICs.