NVMe-to-NVMe Bridge IP Core

The IntelliProp IPC-NV171B-BR NVMe-to-NVMe Bridge IP Core is an inline hardware accelerator engineered to bridge an NVM Express® (NVMe™) host directly to an NVMe™ SSD or storage device[cite: 1]. By managing the full NVMe™ host and target protocol stacks entirely in hardware logic, the core enables real-time packet inspection, command filtering, data encryption, write-blocking, and custom payload manipulation with deterministic, line-rate throughput and near-zero latency penalty[cite: 1].

Architected to operate without requiring host CPU intervention or complex kernel driver overhead, the IPC-NV171B-BR provides a secure, self-contained processing environment between host systems and target media[cite: 1]. The architecture features an open sandbox interface that allows engineering teams to insert proprietary data transformation algorithms, encryption modules, or telemetry tools directly into the PCIe® datapath[cite: 1].

Fully compliant with NVM Express® and PCI Express® specifications, the IPC-NV171B-BR provides a production-hardened foundation for high-assurance storage applications across aerospace and defense, hardware write-blocking tools, inline encryption engines, and enterprise data recording systems across modern FPGA fabrics and ASIC platforms[cite: 1].

Features

• Protocol Compliance: Fully compliant with standard NVM Express® (NVMe™) Revision 1.3/1.4 and PCI Express® (PCIe®) specifications[cite: 1].
• Full Protocol Offload: Hardware state machines manage complete NVMe™ host root complex and target endpoint state machines without software or processor intervention[cite: 1].
• Inline Datapath Manipulation: Direct hardware datapath access enables low-latency packet inspection, command filtering, queue tracking, and real-time data modification[cite: 1].
• Extensible User Sandbox: Provides an open RTL interface for simple integration of custom customer logic, inline AES-256 encryption engines, or data filtering blocks[cite: 1].
• Hardware Write-Blocking Support: Configurable hardware-enforced command filtering capabilities to prevent unauthorized drive modifications in high-security and forensic scenarios[cite: 1].
• Deterministic Throughput: Maintains line-rate PCIe® performance and maximum IOPS throughput for high-bandwidth streaming and playback operations[cite: 1].
• Decoupled System Architecture: Independent clocking and FIFO architectures ensure clean data handling across PCIe® domain boundaries[cite: 1].
• Synchronous Synthesizable RTL: Delivered as production-hardened, fully synchronous Verilog source code or netlist optimized for fast timing closure across leading FPGA fabrics and ASICs[cite: 1].