SAS Target IP Core

Silicon-proven, high-performance Serial Attached SCSI (SAS) target controller IP core that offloads low-level SAS target state machines, primitive parsing, and frame management directly into hardware logic.

The IntelliProp IPC-SS107A-DT SAS Target IP Core is a production-hardened storage controller designed to enable high-speed, reliable target-mode connectivity for custom Serial Attached SCSI (SAS) storage endpoints, enterprise SSD controllers, and array controllers. By offloading complex lower-level SAS protocol state machines, frame parsing, and connection management directly into hardware logic, the core delivers line-rate throughput while eliminating CPU performance overhead.

Architected to manage Serial SCSI Protocol (SSP), Serial ATA Tunneling Protocol (STP), and Serial Management Protocol (SMP) target layer interactions, the IPC-SS107A-DT abstracts low-level protocol mechanics from backend storage logic. This allows engineering teams to construct custom SAS target systems without requiring deep, low-level protocol specialization in primitive handshaking or link state management.

Fully compliant with industry Serial Attached SCSI specifications, the IPC-SS107A-DT features an optimized, fully synchronous synthesizable architecture designed for predictable placement, fast timing closure, and rapid deployment across modern FPGA fabrics and custom ASIC designs.

Features

  • Protocol Compliance: Fully compliant with standard Serial Attached SCSI (SAS) specifications, supporting 3.0 Gbps, 6.0 Gbps, and 12.0 Gbps transmission rates.
  • Multi-Protocol Target Management: Provides full target-side support for Serial SCSI Protocol (SSP), Serial ATA Tunneling Protocol (STP), and Serial Management Protocol (SMP).
  • Hardware Protocol Offload: Fully offloads frame reception, frame validation, CRC generation/checking, and connection state machines into dedicated hardware logic.
  • Automated Link & Speed Negotiation: Integrated hardware state machines manage Out-of-Band (OOB) signaling, speed negotiation, and primitive handshaking automatically.
  • Flexible Backend Memory Interface: Interoperates cleanly with custom NAND flash controllers, DRAM buffers, and system memory bridges.
  • Decoupled Clock Domains: High-efficiency asynchronous FIFO structures ensure seamless, error-free data movement across PHY transceivers and internal logic clock domains.
  • Hardware Bring-Up & Test Features: Includes built-in self-test (BIST) capabilities and loopback test modes to accelerate board bring-up and physical layer validation.
  • Synchronous Synthesizable RTL: Delivered as high-quality, fully synchronous Verilog source code or netlist optimized for predictable placement, routing, and timing

Deliverables

  • Production-Ready Maturity: Extensively verified using a coverage-driven methodology in pseudo-random simulation environments.
  • Flexible Delivery: Fully synthesizable RTL optimized for clean timing closure across modern FPGA and custom ASIC architectures.
  • 100% U.S.-Based Engineering: All design, technical integration, and post-sales support are handled directly by our primary engineering teams operating out of our Longmont, Colorado facilities.
  • Defense-Industry Compliant: Development workflow and documentation adhere to standards required for U.S. defense, aerospace, and ITAR-controlled integration.

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Archived view: https://intellipropipcores.com/ipc-ss107-dt/

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