SAS 1-to-1 Speed Bridge with Sandbox IP

The IntelliProp IPP-SS115A-BR SAS 1-to-1 Speed Bridge with Sandbox IP is a flexible, high-performance hardware solution engineered for inline SAS protocol translation, speed matching, and real-time packet processing. By bridging independent SAS target and initiator links through an open hardware sandbox region, the core allows developers to inject custom data manipulation, frame filtering, encryption, or diagnostic logic directly into the active SAS datapath.

Managing asynchronous clock domains and rate matching between host and target devices, the IPP-SS115A-BR automatically handles lower-level SAS primitives, OOB handshaking, link speed negotiation, and frame encapsulation. The internal sandbox interface exposes standard streaming data and control buses, enabling custom logic to inspect, modify, or block SAS frames without disrupting link management or introducing CPU performance overhead.

Delivered as clean, fully synchronous RTL, the IPP-SS115A-BR provides an ideal foundation for hardware security appliances, protocol converters, line-rate data capture tools, and specialized enterprise storage controllers across modern FPGA fabrics and custom ASIC designs.

Features

• SAS Line Rate Speed Matching: Operates as a transparent 1-to-1 bridge between SAS host initiators and SAS target drives, supporting 3.0 Gbps, 6.0 Gbps, and 12.0 Gbps transmission speeds.
• Integrated User Sandbox Region: Features a clean, modular hardware interface enabling customer-proprietary logic (encryption, filtering, protocol translation, or analytics) to process SAS frames in real time.
• Automated Primitive & Link Handling: Integrated state machines manage lower-level OOB signaling, speed negotiation, primitive translation, and connection handshaking automatically in hardware.
• Protocol Offload & Processing: Handles lower-level SAS frame parsing, CRC checking/generation, and payload buffering directly in dedicated RTL logic.
• Decoupled Clock Domain FIFOs: High-performance asynchronous FIFO architectures ensure seamless data movement across independent transceiver and system clock domains.
• Multi-Protocol Frame Support: Supports transparent bridging for Serial SCSI Protocol (SSP), Serial ATA Tunneling Protocol (STP), and Serial Management Protocol (SMP) frames.
• Hardware Diagnostics & Bring-Up Support: Includes built-in self-test (BIST) state machines and loopback verification modes to accelerate physical board bring-up and system validation.
• Synchronous Synthesizable RTL: Delivered as high-quality, fully synchronous Verilog source code or netlist optimized for predictable placement, routing, and timing closure on leading FPGAs and custom ASICs.